#MEMORY MAPPED REGISTER SOFTWARE#
Hence, to access these registers software should use CXL.io memory read/write cycles for RCRB space-defined register else CXL.io configuration read/write cycles. Whereas for CXL1.1, DVSEC7 (PCIe DVSEC for FlexBus Port) resides in Root Complex Register Blocks (RCRB) space and rest others reside in RciEP defined configuration space. MLD DVSEC: Contains Multi-Logical devices (MLD) feature-specific parametersĪn important point to note here all register spaces defined above exist in PCIe-defined configuration space for CXL2.0 devices.Register Locator DVSEC: Application-defined register blocks.PCIe DVSEC for Flex Bus Port: Critical DVSEC consists of particulars on CXL link training.GPF DVSEC for CXL Devices: Contains Global Persistent Flush (GPF) feature specific parameters.PCIe DVSEC for CXL Devices: Important DVSEC carries information for device attributes like semantics supports, host managed device settings, etc.DVSEC ID associated with capability helps determine the type of CXL capability. Configuration space defined register spaceĬonfiguration Space Defined Register SpaceĪll configuration space registers are identified as PCIe defined designated vendor-specific extended capabilities (DVSEC) registers with DVSEC Vendor ID as h1E98 (reserved for CXL).There are two sets of register space in CXL, one that resides under configuration space and the another set that resides under memory mapped space. In this blog, we will discuss newly introduced registers for the CXL-compliant devices and how they are discovered during the CXL enumeration flow. Hence, the configuration space for CXL1.1 and CXL 2.0 varies. Notably, there is a difference between the discovery of CXL 1.1 versus the CXL 2.0 device.
CXL 2.0 device is exposed as PCIe native endpoint and CXL 1.1 is exposed as root complex integrated endpoints (RCiEP) during software enumeration process. PCIe designed system fabrics rely on software enumeration by Operating System (OS) for device discovery.
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